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INTEGRATED CIRCUITS
DATA SHEET
SAA4998H Field and line rate converter with noise reduction and embedded memory
Product specification 2004 Feb 18
Philips Semiconductors
Product specification
Field and line rate converter with noise reduction and embedded memory
CONTENTS 1 2 2.1 2.2 3 4 5 6 7 8 9 FEATURES GENERAL DESCRIPTION Patent notice Latch-up test QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAMS PINNING CONTROL REGISTER DESCRIPTION LIMITING VALUES THERMAL CHARACTERISTICS 10 11 12 12.1 12.2 12.3 12.4 12.5 12.6 13 14 15 CHARACTERISTICS PACKAGE OUTLINE SOLDERING
SAA4998H
Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods Additional soldering information DATA SHEET STATUS DEFINITIONS DISCLAIMERS
2004 Feb 18
2
Philips Semiconductors
Product specification
Field and line rate converter with noise reduction and embedded memory
1 FEATURES 2 GENERAL DESCRIPTION
SAA4998H
* Motion compensated frame rate upconversion of all 1fH film and video standards up to 292 active input lines per field: - 50 Hz interlaced to 60 Hz progressive {(60p mode for LCD and Plasma Display (PDP) TV} - 50 Hz interlaced to 75 Hz interlaced {75i mode for jumbo screens, Projection TV (PTV)} - 50 Hz interlaced to 100 Hz interlaced (high-end 100 Hz TV) - 50 Hz interlaced to 50 Hz progressive (progressive scan TV and LCD and PDP TV) - 60 Hz interlaced to 60 Hz progressive (progressive scan TV and LCD and PDP TV) - 60 Hz interlaced to 90 Hz interlaced (jumbo screens, PTV) - 60 Hz interlaced to 120 Hz interlaced (multistandard high-end 100 Hz TV) * 480 active lines (NTSC like) or 506 active lines in 50 Hz interlaced to 60 Hz progressive mode * Motion compensated and Edge Dependent De-Interlacing (EDDI)(1) * Motion estimated film mode detection * Motion compensated movie judder cancellation: - 25 Hz 2 : 2 pull-down (PAL) to 60 Hz progressive or 75 Hz interlaced or 100 Hz interlaced or 50 Hz progressive - 30 Hz 2 : 2 pull-down (NTSC) to 60 Hz progressive or 90 Hz interlaced or 120 Hz interlaced - 24 Hz 3 : 2 pull-down (NTSC) to 60 Hz progressive or 90 Hz interlaced or 120 Hz interlaced * Variable vertical sharpness enhancement * High quality vertical zoom * Motion compensated temporal noise reduction with after-imaging cancellation * Split screen demonstration mode * 2 Mbaud serial interface (SNERT) * Embedded 2 x 2.9-Mbit DRAM * Full 8-bit accuracy * Memory buffer for Picture-In-Picture (PIP) * Lead-free package.
The SAA4998H is a high performance video processor featuring Natural MotionTM(2), for all global TV standards (PAL, NTSC and SECAM). It is used together with the picture improvement processor SAA4978H and SAA4979H. The SAA4998H is an advanced version of the SAA4993H. By embedding the field memories it reduces the part count of the realized concept from 4 to 6 parts to only 2 parts and reduces the package size from a QFP160 to a QFP100. The full FALCONIC mode uses full motion estimation and motion compensation on 1/4 pixel accuracy to perform * Frame rate upconversion * Film mode detection * Movie judder cancellation * Dynamic Noise Reduction (DNR) * Edge Dependent De-Interlacing (EDDI). The motion compensated de-interlacer is improved with a new patented Edge Dependent De-Interlacing (EDDI) method. This avoids jagged edges of diagonal lines. The better de-interlacer leads to a significant better performance of progressive as well as interlaced output formats. A 60 Hz progressive output frame rate can be generated for 50 Hz PAL sources to enable the use of 60 Hz LCD or PDP panels in PAL regions. 50 Hz interlaced to 75 Hz interlaced and 60 Hz interlaced to 90 Hz interlaced can be generated to achieve an increased number of lines and hence a reduction of line visibility for jumbo screens and PTV applications. The embedded memory can be used to synchronize the main channel and the 2nd channel for PIP and double window applications. This avoids to add additional buffer memory devices to the application. For demonstration purposes a split screen mode to show the Dynamic Noise Reduction (DNR) function, natural motion, and EDDI is available. The estimated motion vectors can be made visible by colour overlay mode. The SAA4998H supports a Boundary Scan Test (BST) circuit in accordance with "IEEE Std. 1149.1".
(1) EDDI is protected with two patents of Koninklijke Philips Electronics N.V.
(2) Natural Motion is a trademark of Koninklijke Philips Electronics N.V.
2004 Feb 18
3
Philips Semiconductors
Product specification
Field and line rate converter with noise reduction and embedded memory
2.1 Patent notice 2.2 Latch-up test
SAA4998H
Notice is herewith given that the subject integrated circuit uses one or more of the following US patents and that each of these patents may have corresponding patents in other jurisdictions. US 4740842, US 5929919, US 6034734, US 5534946, US 5532750, US 5495300, US 5903680, US 5365280, US 5148269, US 5072293, US 5771074, and US 5302909. 3 QUICK REFERENCE DATA SYMBOL VDDD VDDA VDDM VDDS VDDE VDDP IDD analog supply voltage field memory supply voltage SRAM supply voltage external supply voltage (output pads) PARAMETER core supply voltage (internal rail)
Latch-up test in accordance with "Latch-up Resistance and Maximum Ratings Test; SNW-FQ-303"; the SAA4998H fulfils the requirements.
MIN. 1.65
TYP. 1.8
MAX. 1.95 V
UNIT
3.0
3.3
3.6
V
high supply voltage of internal field memories sum of supply current at 1.8 V supply voltage pins at 3.3 V supply voltage pins - - - 0 180 6 32 - - - 33.3 70 mA mA MHz C
fCLK Tamb 4
operating clock frequency ambient temperature
ORDERING INFORMATION TYPE NUMBER PACKAGE NAME QFP100 DESCRIPTION plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm VERSION SOT317-2
SAA4998H
2004 Feb 18
4
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YA0 to YA7 55 to 62 DYNAMIC NOISE REDUCTION FIELD MEMORY 2 MEMORY CONTROL FIELD MEMORY 3 VD SNCL SNDA SNRST 94 41 34 33 SNERT INTERFACE COMPRESS DECOMPRESS ACV RST PIPON TWOFMON REA IE REF 25 32 36 50 63 64 67 MPR LEFT 31 30 29 28 27 83 UPCONVERSION BST/ TEST SPM vectors MPR RIGHT VERTICAL PEAKING VERTICAL ZOOM CONTROL DE-INTERLACER WITH EDDI MUX MUX
5
Philips Semiconductors
Field and line rate converter with noise reduction and embedded memory
BLOCK DIAGRAMS
5
68, 69, 71 to 76 95, 100, 1, 2, 5 to 8
YF7 to YF0
TPM
ESM
TCK TDO TDI TMS TRSTN CLK32
YG7 to YG0
MOTION ESTIMATOR vectors
SAA4998H
LUMINANCE PART
coc001
Product specification
SAA4998H
Fig.1 Block diagram luminance part in full FALCONIC mode.
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FIELD MEMORY 2 FIELD MEMORY 3 COMPRESS/ FORMAT 42 to 47, 53, 54 DECOMPRESS/ REFORMAT DECOMPRESS/ REFORMAT UVA0 to UVA7 DNR
Philips Semiconductors
Field and line rate converter with noise reduction and embedded memory
6
MPR LEFT
vectors MPR RIGHT UPCONVERSION VERTICAL ZOOM FORMAT 78 to 81, 88, 89, 92, 93 9 to 13, 17 to 19
UVF7 to UVF0
UVG7 to UVG0
SAA4998H
CHROMINANCE PART
coc002
Product specification
SAA4998H
Fig.2 Block diagram chrominance part in full FALCONIC mode.
Philips Semiconductors
Product specification
Field and line rate converter with noise reduction and embedded memory
6 PINNING SYMBOL YG5/DPIP5 YG4/DPIP4 VDDE VSSE YG3/DPIP3 YG2/DPIP2 YG1/DPIP1 YG0/DPIP0 UVG7/QPIP7 UVG6/QPIP6 UVG5/QPIP5 UVG4/QPIP4 UVG3/QPIP3 n.c./LLC VSSE n.c./SWCK2 UVG2/QPIP2 UVG1/QPIP1 UVG0/QPIP0 n.c./RSTW2 n.c./OIE2 n.c./IE2 VDDP n.c./WE2 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 TYPE output/input output/input supply ground output/input output/input output/input output/input output output output output output input ground input output output output input input input supply input DESCRIPTION(1)(2)(3) PIP mode disabled: bus G luminance output bit 5; PIP mode enabled: PIP data input bit 5 PIP mode disabled: bus G luminance output bit 4; PIP mode enabled: PIP data input bit 4 supply voltage of output pads (3.3 V) ground of output pads PIP mode disabled: bus G luminance output bit 3; PIP mode enabled: PIP data input bit 3 PIP mode disabled: bus G luminance output bit 2; PIP mode enabled: PIP data input bit 2 PIP mode disabled: bus G luminance output bit 1; PIP mode enabled: PIP data input bit 1 PIP mode disabled: bus G luminance output bit 0 (LSB); PIP mode enabled: PIP data input bit 0 (LSB)
SAA4998H
PIP mode disabled: bus G chrominance output bit 7 (MSB); PIP mode enabled: PIP data output bit 7 (MSB) PIP mode disabled: bus G chrominance output bit 6; PIP mode enabled: PIP data output bit 6 PIP mode disabled: bus G chrominance output bit 5; PIP mode enabled: PIP data output bit 5 PIP mode disabled: bus G chrominance output bit 4; PIP mode enabled: PIP data output bit 4 PIP mode disabled: bus G chrominance output bit 3; PIP mode enabled: PIP data output bit 3 PIP mode disabled: not connected; PIP mode enabled: line locked clock signal for PIP mode ground of output pads PIP mode disabled: not connected; PIP mode enabled: serial write clock for PIP memory PIP mode disabled: bus G chrominance output bit 2; PIP mode enabled: PIP data output bit 2 PIP mode disabled: bus G chrominance output bit 1; PIP mode enabled: PIP data output bit 1 PIP mode disabled: bus G chrominance output bit 0 (LSB); PIP mode enabled: PIP data output bit 0 (LSB) PIP mode disabled: not connected; PIP mode enabled: write reset clock for PIP memory PIP mode disabled: not connected; PIP mode enabled: output enable for PIP memory output QPIPx PIP mode disabled: not connected; PIP mode enabled: input enable for PIP memory high supply voltage of the internal field memories (3.3 V) PIP mode disabled: not connected; PIP mode enabled: write enable for PIP memory 7
2004 Feb 18
Philips Semiconductors
Product specification
Field and line rate converter with noise reduction and embedded memory
SYMBOL ACV/RE2 n.c./RSTR2 TRSTN TMS TDI TDO TCK RST SNRST SNDA VDDE PIPON VSSM VDDM VSSM VDDM SNCL UVA0 UVA1 UVA2 UVA3 UVA4 UVA5 VDDD VSSD TWOFMON VDDS VSSS UVA6 UVA7 YA0 YA1 YA2 YA3 YA4 YA5 YA6 YA7 REA 2004 Feb 18 PIN 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 TYPE output/input input input input input 3-state input input input input/output supply input ground supply ground supply input input input input input input input supply ground input supply ground input input input input input input input input input input output DESCRIPTION(1)(2)(3) PIP mode disabled: active video output; PIP mode enabled: read enable for PIP memory PIP mode disabled: not connected; PIP mode enabled: read reset for PIP memory
SAA4998H
boundary scan test reset input (active LOW); with internal pull-up resistor boundary scan test mode select input; with internal pull-up resistor boundary scan test data input; with internal pull-up resistor boundary scan test data output boundary scan test clock input; with internal pull-up resistor reset input; see Fig.4 SNERT bus reset input; with internal pull-down resistor SNERT bus data input and output; with internal pull-down resistor supply voltage of output pads (3.3 V) PIP mode enable input field memory ground supply voltage of the internal field memories (1.8 V) field memory ground supply voltage of the internal field memories (1.8 V) SNERT bus clock input; with internal pull-down resistor bus A chrominance input bit 0 (LSB) bus A chrominance input bit 1 bus A chrominance input bit 2 bus A chrominance input bit 3 bus A chrominance input bit 4 bus A chrominance input bit 5 core supply voltage (1.8 V) core ground to be connected to ground supply voltage of the internal SRAMs (1.8 V) ground of the internal SRAMs bus A chrominance input bit 6 bus A chrominance input bit 7 (MSB) bus A luminance input bit 0 (LSB) bus A luminance input bit 1 bus A luminance input bit 2 bus A luminance input bit 3 bus A luminance input bit 4 bus A luminance input bit 5 bus A luminance input bit 6 bus A luminance input bit 7 (MSB) read enable output for bus A 8
Philips Semiconductors
Product specification
Field and line rate converter with noise reduction and embedded memory
SYMBOL IE VDDD VSSD REF YF7 YF6 VSSE YF5 YF4 YF3 YF2 YF1 YF0 VDDE UVF7 UVF6 UVF5 UVF4 VSSE CLK32 VDDS VSSS VDDD VSSD UVF3 UVF2 VSSA VDDA UVF1 UVF0 VD YG7/DPIP7 VDDM VSSM PIN 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 TYPE input supply ground input output output ground output output output output output output supply output output output output ground input supply ground supply ground output output ground supply output output input output/input supply ground input enable for PIP mode core supply voltage (1.8 V) core ground read enable input for bus F and G; note 4 bus F luminance output bit 7 (MSB) bus F luminance output bit 6 ground of output pads bus F luminance output bit 5 bus F luminance output bit 4 bus F luminance output bit 3 bus F luminance output bit 2 bus F luminance output bit 1 bus F luminance output bit 0 (LSB) supply voltage of output pads (3.3 V) bus F chrominance output bit 7 (MSB) bus F chrominance output bit 6 bus F chrominance output bit 5 bus F chrominance output bit 4 ground of output pads system clock input (32 MHz) supply voltage of the internal SRAMs (1.8 V) ground of the internal SRAMs core supply voltage (1.8 V) core ground bus F chrominance output bit 3 bus F chrominance output bit 2 analog ground of the internal PLL analog supply voltage of the internal PLL (1.8 V) bus F chrominance output bit 1 bus F chrominance output bit 0 (LSB) DESCRIPTION(1)(2)(3)
SAA4998H
vertical display synchronization input (reset for field memories) PIP mode disabled: bus G luminance output bit 7 (MSB); PIP mode enabled: PIP data input bit 7 (MSB) supply voltage of the internal field memories (1.8 V) field memory ground
2004 Feb 18
9
Philips Semiconductors
Product specification
Field and line rate converter with noise reduction and embedded memory
SYMBOL VDDM VSSM YG6/DPIP6 Notes 1. Not used input pins should be connected to ground. PIN 98 99 100 TYPE supply ground output/input field memory ground PIP mode disabled: bus G luminance output bit 6; PIP mode enabled: PIP data input bit 6 DESCRIPTION(1)(2)(3) supply voltage of the internal field memories (1.8 V)
SAA4998H
2. Because of the noisy characteristic of the supply voltage of output pads (VDDE), it is recommended not to connect VDDE directly at the high supply voltage of the intern field memories (VDDP). All pins VDDE should be buffered as close as possible to the device. VDDP needs a low noise supply voltage, therefore, it is recommended that VDDP has to be separated from VDDE by an external filter structure. Because of the high working frequency of the device, it is also recommended to filter the core supply voltage (VDDD). All pins VDDD should be buffered as close as possible to the device. 3. VSSD, VSSM and VSSS are connected internally. 4. REF rising edge must be after rising edge of SNRST in order to be detected.
2004 Feb 18
10
Philips Semiconductors
Product specification
Field and line rate converter with noise reduction and embedded memory
SAA4998H
100 YG6/DPIP6
95 YG7/DPIP7
83 CLK32
98 VDDM
96 VDDM
93 UVF0
92 UVF1
89 UVF2
88 UVF3
81 UVF4 80 UVF5 79 UVF6 78 UVF7 77 VDDE 76 YF0 75 YF1 74 YF2 73 YF3 72 YF4 71 YF5 70 VSSE 69 YF6 68 YF7 67 REF 66 VSSD 65 VDDD 64 IE 63 REA 62 YA7 61 YA6 60 YA5 59 YA4 58 YA3 57 YA2 56 YA1 55 YA0 54 UVA7 53 UVA6 52 VSSS 51 VDDS TWOFMON 50
001aaa057
99 VSSM
97 VSSM
86 VDDD
91 VDDA
84 VDDS UVA5 47
87 VSSD
90 VSSA
85 VSSS
YG5/DPIP5 YG4/DPIP4 VDDE VSSE YG3/DPIP3 YG2/DPIP2 YG1/DPIP1 YG0/DPIP0 UVG7/QPIP7
1 2 3 4 5 6 7 8 9
UVG6/QPIP6 10 UVG5/QPIP5 11 UVG4/QPIP4 12 UVG3/QPIP3 13 n.c./LLC 14 VSSE 15 n.c./SWCK2 16 UVG2/QPIP2 17 UVG1/QPIP1 18 UVG0/QPIP0 19 n.c./RSTW2 20 n.c./OIE2 21 n.c./IE2 22 VDDP 23 n.c./WE2 24 ACV/RE2 25 n.c./RSTR2 26 TRSTN 27 TMS 28 TDI 29 TDO 30 TCK 31 RST 32 SNRST 33 SNDA 34 VDDE 35 PIPON 36 VSSM 37 VDDM 38 VSSM 39 VDDM 40 SNCL 41 UVA0 42 UVA1 43 UVA2 44 UVA3 45 UVA4 46 VDDD 48 VSSD 49
SAA4998H
Fig.3 Pin configuration.
2004 Feb 18
11
82 VSSE
94 VD
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Field and line rate converter with noise reduction and embedded memory
NAME DNR/peaking/colour Kstep10 Kstep0 Kstep1 Kstep32 Kstep2 Kstep3 Kstep54 Kstep4 Kstep5 Kstep76 Kstep6 Kstep7 Gain_fix_y FixvalY GainY FixY Gain_fix_uv FixvalUV GainUV FixUV
SNERT READ/ ADDRESS 76543210 WRITE(1) (HEX)
DESCRIPTION(2)
010
write; S X X X X set LUT value: k = 116 if difference below (0 to 15) XXXX set LUT value: k = 18 if difference below (0 to 15) X X X X set LUT value: k = 28 if difference below (0 to 30 in multiples of 2) XXXX set LUT value: k = 38 if difference below (0 to 30 in multiples of 2) X X X X set LUT value: k = 48 if difference below (0 to 60 in multiples of 4) XXXX set LUT value: k = 58 if difference below (0 to 60 in multiples of 4) X X X X set LUT value: k = 68 if difference below (0, 8, 16, 24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112 or 120) XXXX set LUT value: k = 78 if difference below (0, 8, 16, 24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112 or 120) X X X X set fixed Y value; used when FixY = 1 or in left part of split screen (0, 116 to 1416 or 1616) XXX X set gain in difference signal for adaptive DNR Y (18, 14, 12, 1, 2 or 4) select fixed Y (adaptive or fixed) (full screen) X X X X set fixed UV value; used when FixUV = 1 or in left part of split screen (0, 116 to 1416 or 1616) XXX X set gain in difference signal for adaptive DNR UV (18, 14, 12, 1, 2 or 4) select fixed UV (adaptive or fixed) (full screen)
011
write; S
012
write; S
013
write; S
014
write; S
015
write; S
Product specification
SAA4998H
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Field and line rate converter with noise reduction and embedded memory
NAME Peak_Vcomp VecComp NoiseShape PeakCoef DNR_Colour_mode ColourIn ColourOut NrofFMs ColOvl SlaveUVtoY DnrSplit DnrHpon Vertical zoom Zoom1 ZoomSt98
DESCRIPTION(2)
018
write; F X X zoom line step bits 9 and 8; line step = vertical distance between successive output lines; usable range = 0 to 2 frame lines; resolution 1256 frame line XX zoom start position bits 9 and 8; start position = vertical position of the top display line; usable range = 1 to 3 frame lines; resolution 1256 frame line Product specification
ZoomPo98
Zoom2 ZoomSt70 Zoom3 ZoomPo70
019 01A
write; F X X X X X X X X zoom line step bits 7 to 0 (see above) write; F X X X X X X X X zoom start position bits 7 to 0 (see above)
SAA4998H
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Field and line rate converter with noise reduction and embedded memory
NAME Zoom4 ZoomEnVal ZoomDiVal De-interlacer Proscan1 KlfLim KlfOfs
DESCRIPTION(2)
01C
write; S X X X X limitation of recursion factor in calculation of original line positions: (1 to 16); 1 limits to almost full recursion, 16 limits to no recursion XXXX The transfer curve of the de-interlacing filter coefficient is determined by the difference (Diff) between a line in the input field and the counterpart in the previous field shifted over the estimated motion vector. KlfOfs determines the bias of the transfer curve for the original input line, such that coefficient = KlfOfs + F(Diff), where the function F is calculated in the SAA4998H. The bias can take a value in the range (0 to 15), representing decreasing filter strength.
SAA4998H
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Field and line rate converter with noise reduction and embedded memory
NAME Proscan4 PlfThr
DESCRIPTION(2)
AdRecOut ProDiv
KplOff Proscan5 VecRbf 0CB write; S
X
FadDiv KplFad
Proscan6 EddiOut EddiDemo EddiCmp
0F0
write; S
SAA4998H
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Field and line rate converter with noise reduction and embedded memory
NAME Proscan7 EddiMR EddiED
DESCRIPTION(2)
EddiDif
XXXX
Proscan8 EddiFil
0F2
write; S
EddiLng
SAA4998H
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Field and line rate converter with noise reduction and embedded memory
NAME TotalPxDiv8
DESCRIPTION(2)
X X X X X X X X Total number of pixels per line divided-by-8 (80 to 128, corresponds to 640 to 1024 pixels). The horizontal blanking interval is calculated as TotalPxDiv8 - 2 x NrBlks and has to be in the range from 12 to 124 (corresponds to 96 to 992 pixels). Conclusion: TotalPxDiv8 has to be set to 12 + 2 x NrBlks < TotalPxDiv8 < 124 + 2 x NrBlks and NrBlks TotalPxDiv8 - 124 TotalPxDiv8 - 12 has to be set to ----------------------------------------------- < NrBlks < -------------------------------------------2 2 X X X shift of REA signal in number of pixels (0, +1, +2, +3, -4, -3, -2 or -1) X X X reserved XXX reserved X power-on reset command, to be set high temporarily during start-up (normal or reset); note 3 X X X X X X X X 8-bit scaling factor for EggSliceMix, EggSliceRgt and global activity (the same factor for all registers). ScalingFactor output value (n+1) = ----------------------------------- x output value (n) 128
REaShift WEbdREceShift WEbdShift REceShift POR ScalingFactor
023 024
write; S write; S
025 0D6
write; S write; S
Product specification
SAA4998H
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Field and line rate converter with noise reduction and embedded memory
NAME Mode control Control1 EstMode
DESCRIPTION(2)
026
write; F X Set estimator mode; 0 = line alternating use of left and right estimator: use in progressive scan except with vertical compress. 1 = field alternating use of left and right estimator: use in field doubling and progressive scan with vertical compress. X XX set film mode; 0 = video camera mode; 1 = film mode select upconversion quality; 00 = full, 01 = economy (DPCM), 10 = single memory with motion compensation, 11 = single memory without motion compensation set matrix output mode; 1 = double output, disabling vertical peaking; 0 = normal single output mode; this bit setting is the AND function of BusGControl bits Master enable for embrace mode (off or on); SwapMpr in control2 should be at `swap' position to really cross-switch FM1 and FM3 field outputs. Should be set to logic 0 except in film mode and FM3 is present. set memory compression (luminance DPCM) (off or on) set memory decompression (luminance DPCM) (off or on)
FilmMode UpcMode
MatrixOn
X
EmbraceOn
X
Product specification
SAA4998H
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Field and line rate converter with noise reduction and embedded memory
NAME Control2 QQcurr
DESCRIPTION(2)
QQprev
FldStat
X
FieldWeYUV
X
OddFM1 SwapMpr X
X
VecOffs
XX
Product specification
SAA4998H
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Field and line rate converter with noise reduction and embedded memory
NAME Control3 OddLeft OrigFmEnY
DESCRIPTION(2)
IntpFmEnY
X
FillTPM
X
VertOffsDNR
XX
SAA4998H
X X X X X X temporal interpolation factor used in luminance upconverter; value ranges from 0 (for current field position) to 32 (for previous field position)
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Field and line rate converter with noise reduction and embedded memory
NAME Upconv2 YVecClip
DESCRIPTION(2)
RollBack Upconv3 MelzLfbm Melzmemc 02B
F write; S
MelDeint
X
MixCtrl
XXXXX
UpcColShiFac
0C4
write; F
X X X X X X temporal interpolation factor used in chrominance upconverter; value ranges from 0 (for current field position) to 32 (for previous field position) X X X Number of consecutive lines to have bad egg-slice values before upconverter goes into protection mode (0, 1, 2, 4, 8, 16, 32 or 64). A value of 0 switches off the possibility to go into protection. X mode switch on left side of the screen; 0 (natural motion); 1 (digital scan-like processing) Product specification
Upconv4 LfIndex
0C5
write; S
MCDemo EggSlice1 EggStartLine 0C6 write; S
SAA4998H
X X X X X X X X Reference line number at which the egg slice measurement should start. SAA4998H defines a window internally as number of lines between EggStartLine and (MaxRefLine - EggStartLine).
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Field and line rate converter with noise reduction and embedded memory
NAME EggSlice2 EggSlcThr EggRelInd
DESCRIPTION(2)
SafeShiFac Motion estimator Motest1 PenOdd SpcThr
0C8
write; F
02C
write; S X X X additional penalty on vector candidates with odd vertical component (0, 8, 16, 32, 64, 128, 256 or 511) XXX Active when EstMode = 0; replace the spatial prediction of one estimator (left or right) by that of the other if the match error of the former exceeds that of the latter by more than (0, 8, 16, 32, 64, 128, 256 or 511). A higher threshold means the two estimators are very independent. Active when EstMode = 0; select as estimated vector the output of the right estimator unless its match error exceeds that of the left estimator by more than (0, 8, 16 or 32). This parameter should normally be set to logic 0.
SAA4998H
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Field and line rate converter with noise reduction and embedded memory
NAME Motest3 MotShiFac
DESCRIPTION(2)
Motest4 PenRng
Product specification
SAA4998H
write zeros in the temporal prediction memory (no writing or writing zeros)
X X X X X X X X blocks having an activity value below or equal to this threshold are counted as having LOW activity X X X X X X X X blocks having an activity value above this threshold are counted as having HIGH activity
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Field and line rate converter with noise reduction and embedded memory
NAME LeftBorder LeftBorder WinNullWrite RightBorder TopBorder BottomBorder Candidate1 Candidat1 Update1 Penalty1 Candidate2 Candidat2 Update2 Penalty2 Candidate3 Candidat3 Update3 Penalty3 Candidate4 Candidat4 Update4 Penalty4
DESCRIPTION(2)
SAA4998H
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Field and line rate converter with noise reduction and embedded memory
NAME Candidate5 Candidat5 Update5 Penalty5 Candidate6 Candidat6 Update6 Penalty6 Candidate7 Candidat7 Update7 Penalty7 Candidate8 Candidat8 Update8 Penalty8 PZpositionLeftUppX PZpositionLeftUppY
DESCRIPTION(2)
X X X X X X X position of LeftUpp measurement point for pan-zoom calculations (resolution: 16 pixels) X X X X X X X Y position of LeftUpp measurement point for pan-zoom calculations (resolution: 4 lines) X X X X X X X position of RightLow measurement point for pan-zoom calculations (resolution: 16 pixels) X X X X X X X Y position of RightLow measurement point for pan-zoom calculations (resolution: 4 lines) X X X X X X X X X start value of pan-zoom vectors Product specification
SAA4998H
PZpositionRightLowX 09A PZpositionRightLowY 09B PZvectorStartX 09C
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Field and line rate converter with noise reduction and embedded memory
NAME PZvectorDeltaX PZvectorStartY PZvectorDeltaY Read data; note 3 GlobalMSEmsb GlobalMSElsb
DESCRIPTION(2)
X X X X X X X X X delta value of pan-zoom vectors X X X X X X X X Y start value of pan-zoom vectors X X X X X X X X Y delta value of pan-zoom vectors
0A0 0A1
read; F read; F
X X X X X X X X Global Mean Square Error (MSE) = summation within a field period of X X X X X X X X squared differences in comparing vector shifted video from frame memory (FM2/3) with new field input (FM1) in those lines coinciding with new field lines. The window for the measurement is kept at 40 pixels horizontal and 20 field lines vertical from the border of the video. Measurements is only done in fields where the de-interlacer is active, otherwise reading is zero. In field doubling mode, MSE is zero at the end of every new input field. X X X X X X X X Global Motion Trajectory Inconsistency (MTI) = summation within a X X X X X X X X field period of squared differences comparing shifted video from frame memory (FM2/3 output) with filtered data that is rewritten to the frame memory (FM2/3 input) in those lines coinciding with new field lines. The window for the measurement is kept at 40 pixels horizontal and 20 field lines vertical from the border of the video. Measurement is done only in fields where de-interlacer is active, otherwise reading is zero; in field doubling mode, MTI is zero at the end of every new input field. X X X X X X X X global activity (ACT) = summation over a field period of the horizontal X X X X X X X X plus the vertical components of the vectors of all blocks X X X X X X X X Vector temporal consistency = summation over a field period of absolute differences of horizontal plus vertical components of vectors newly estimated for each block compared with those vectors estimated in the previous run at the same spatial block position. It should be noted that a lower figure implies better consistency. X X X X X X X X Vector spatial consistency = summation over a field period of absolute differences of horizontal and vertical components of vectors compared with those of the neighbour blocks (L, R, U and D); in the comparison, all vector data is used from the previous estimator run. It should be noted that a lower figure implies better consistency. X X X X X X X X burst error count (number of burst errors)
GlobalMTImsb GlobalMTIlsb
0A2 0A3
read; F read; F
Product specification
SAA4998H
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Field and line rate converter with noise reduction and embedded memory
NAME LeastErrSum
DESCRIPTION(2)
X X X X X X X X least error sum (summation over a field period of the smallest match error that the estimator has found for each block: indicates reliability of the estimation process) X X X X X X X X Y vector range error count (number of vectors that have a vertical component that is out of range for upconversion at the chosen temporal position) (15 to 8) X X X X X X X X Y vector range error count (7 to 0) X X X X X X X X read out of [number of input (run-) lines - 40] used in previous field X X X X X X X X Write of [number of input (run-) lines - 40] to be used in new field (actual maximum number of input lines in normal operation: 292; register value 252). Nominally this is to be set as an exact copy of the value read from RefLineCountPrev before a new field starts. In case the effective number of input (run-) lines has increased, RefLineCountNew should, for one field, be set to 255. This will occur e.g. with decreasing vertical zoom magnification or changing from 525 lines video standard to 625 lines standard. If this is not done, a deadlock will occur with too few lines processed correctly by the motion estimator. X X X X X X X X pan-zoom vector 0 (8-bit X value)
YvecRangeErrCntmsb 0AA
read; F
YvecRangeErrCntlsb RefLineCountPrev RefLineCountNew
0AB 0AC 0AD
read; F read; F write; F
Product specification
SAA4998H
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Field and line rate converter with noise reduction and embedded memory
NAME PanZoomVec3-X PanZoomVec3-Y PanZoomVec4-X PanZoomVec4-Y PanZoomVec5-X PanZoomVec5-Y PanZoomVec6-X PanZoomVec6-Y PanZoomVec7-X PanZoomVec7-Y PanZoomVec8-X PanZoomVec8-Y EggSliceRgtMSB EggSliceRgtLSB EggSliceMixMSB EggSliceMixLSB SafeFbLine EggBinGoodness
DESCRIPTION(2)
X X X X X X X X pan-zoom vector 2 (8-bit X value) X X X X X X X pan-zoom vector 3 (7-bit Y value) X X X X X X X X pan-zoom vector 4 (8-bit X value) X X X X X X X pan-zoom vector 4 (7-bit Y value) X X X X X X X X pan-zoom vector 5 (8-bit X value) X X X X X X X pan-zoom vector 5 (7-bit Y value) X X X X X X X X pan-zoom vector 6 (8-bit X value) X X X X X X X pan-zoom vector 6 (7-bit Y value) X X X X X X X X pan-zoom vector 7 (8-bit X value) X X X X X X X pan-zoom vector 7 (7-bit Y value) X X X X X X X X pan-zoom vector 8 (8-bit X value) X X X X X X X pan-zoom vector 8 (7-bit Y value) X X X X X X X X result of right pixels egg-slice detector (15 to 8) X X X X X X X X result of right pixels egg-slice detector (7 to 0) X X X X X X X X result of mixed pixels egg-slice detector (15 to 8) X X X X X X X X result of mixed pixels egg-slice detector (7 to 0) X X X X X X X X reference line number (divided by two) at which the upconverter goes into protection mode X X X X X X X X Goodness of the four egg-slice sections, from top to bottom, 2 bits per section. Each section is represented with 2 bits in this register, where bits 0 and 1 represent the top section and bits 6 and 7 represent the lowest of the 4 sections. Each pair of bits indicate 00 = (ESR > 34ESM), 01 = (12ESM < ESR 34ESM), 10 = (14ESM < ESR 12ESM), 11 = (ESR 14ESM). X X X X X X X X number of blocks having low activity X X X X X X X X number of blocks having high activity
LoActCnt HiActCnt NullErrSum
0D3 0D4 0D5
read; F read; F read; F
Product specification
X X X X X X X X sum of errors for the null candidate over the complete field; when no null candidate is selected a value of FFH will be read
SAA4998H
Philips Semiconductors
Product specification
Field and line rate converter with noise reduction and embedded memory
Notes
SAA4998H
1. S means semi static, used at initialization or mode changes; F means field frequent, in general updated in each display field. 2. Selectable items are marked bold. 3. Almost all of the R(ead) and W(rite) registers of SAA4998H are double buffered. The write registers are latched by a signal called New_field. New_field gets set, when REF rises after SNRST (New_field is effectively at the start of active video). The read registers are latched by a signal called Reg_upd. Reg_upd gets set, when half the number of active pixels of the fourth line of vertical blanking have entered the SAA4998H (Reg_upd will effectively be active 312 lines after the REA has ended). The only exception are the registers which are not double buffered, these are as follows: a) Write register 025H: power_on_reset b) Write register 02FH, bit 1: CndSet c) Read register 0B0H to 0BFH, 0AEH and 0AFH: pan_zoom_vectors, including FalconIdent (= 0), StatusJump0 and StatusJump1. 8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VDDD VDDA VDDM VDDS VDDE VDDP Vi Io Tstg Tj Vesd PARAMETER core supply voltage (internal rail) analog supply voltage field memory supply voltage SRAM supply voltage external supply voltage (output pads) high supply voltage of internal field memories input voltage of all I/O pins output current storage temperature junction temperature electrostatic discharge voltage on all pins MM; note 2 HBM; note 3 Notes 1. Only valid, if VDDE is present. 2. In accordance with "Transient energy (ESD machine model); SNW-FQ-302B" class C, discharging a 200 pF capacitor via a 0.75 H series inductance. 3. In accordance with "Transient energy (ESD human body model); SNW-FQ-302A" class 2, discharging a 100 pF capacitor via a 1.5 k series resistor. 9 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) Rth(j-c) PARAMETER thermal resistance from junction to ambient thermal resistance from junction to case CONDITIONS in free air VALUE 45 10 UNIT K/W K/W -0.5 - -40 0 -400 -3000 +6(1) 4 +125 125 +400 +3000 V mA C C V V -0.5 +4.6 V CONDITIONS MIN. -0.5 MAX. +2.5 V UNIT
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Philips Semiconductors
Product specification
Field and line rate converter with noise reduction and embedded memory
10 CHARACTERISTICS VDDE = 3.0 to 3.6 V; Tamb = 0 to 70 C; unless otherwise specified. SYMBOL Supplies VDDD VDDA VDDM VDDS VDDE VDDP IDD core supply voltage (internal rail) analog supply voltage field memory supply voltage SRAM supply voltage external supply voltage (output pads) high supply voltage of internal field memories sum of supply current at 1.8 V supply voltage pins at 3.3 V supply voltage pins General VOH VOL VIH VIL IOH IOL Ci ILI IOZ td(o) th(o) Inputs tr tf tsu(i) th(i) tr tf Tcy rise time fall time input set-up time input hold time see Fig.5; note 3 see Fig.5; note 3 - - 6 2 - - 40 30 - - - - - - - - HIGH-level output voltage LOW-level output voltage HIGH-level input voltage LOW-level input voltage HIGH-level output current LOW-level output current input capacitance input leakage current note 1 -0.5 < Vo < 3.6 10 ns slew rate output; VOH = VDDE - 0.4 V 10 ns slew rate output; VOL = 0.4 V VDDE - 0.4 - 2 - -4 - - - - - 4 - - - - - - - - - - - - - 180 6 3.0 3.3 1.65 1.8 PARAMETER CONDITIONS MIN.
SAA4998H
TYP.
MAX.
UNIT
1.95
V
3.6
V
- - - 0.4 - 0.8 - 4 8 1
mA mA
V V V V mA mA pF A A ns ns
Outputs; see Fig.5; note 2 output current in 3-state mode output delay time output hold time 1 23 - 30 30 - - 4 4 60 39
ns ns ns ns
Input CLK32; see Fig.5 rise time fall time duty factor cycle time ns ns % ns
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Philips Semiconductors
Product specification
Field and line rate converter with noise reduction and embedded memory
SYMBOL BST interface; see Fig.6 Tcy(BST) tsu(i)(BST) th(i)(BST) th(o)(BST) td(o)(BST) tSNRST(H) BST cycle time input set-up time input hold time output hold time output delay - 3 6 4 - 500 200 0.5 53 10 30 - 210 1 - - - - - - - - - - - - PARAMETER CONDITIONS MIN.
SAA4998H
TYP.
MAX. - - - - 30 - - 1 - - - 330 -
UNIT s ns ns ns ns
SNERT interface; see Fig.7 SNRST pulse HIGH time ns ns s ns ns ns ns ns td(SNRST-SNCL) delay SNRST pulse to SNCL LOW time Tcy(SNCL) tsu(i)(SNCL) th(i)(SNCL) th(o) td(o) to(en) Notes 1. All inputs except inputs with internal pull-up or pull-down resistor. These inputs have an absolute leakage current of maximum 50 A. 2. Timing characteristics are measured with CL = 15 pF. 3. All inputs except SNERT interface inputs, CLK32 input and BST/TEST inputs. SNCL cycle time input set-up time to SNCL input hold time to SNCL output hold time output delay output enable time
stable power supply
CLK32
RST
10 cycles of CLK32
coc003
Fig.4 Timing for RST input.
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Philips Semiconductors
Product specification
Field and line rate converter with noise reduction and embedded memory
SAA4998H
handbook, full pagewidth
tf 90%
tr 90% 1.5 V 10%
CLOCK 10%
INPUT DATA
MHB175
tsu(i)
th(i)
OUTPUT DATA
data valid th(o)
data transition period
td(o)
Fig.5 Data input/output timing diagram.
handbook, full pagewidth
Tcy(BST)
TCK
TDI, TMS t su(i)(BST) t h(i)(BST)
MHB649
TDO t h(o)(BST) t d(o)(BST)
Fig.6 Boundary scan test interface timing diagram.
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Philips Semiconductors
Product specification
Field and line rate converter with noise reduction and embedded memory
SAA4998H
SNCL
write sequence: SNDA read sequence: SNDA driven by master SNDA driven by SAA4998H a0 a1 a2 a3 a4 a5 a6 a7 a0 a1 a2 a3 a4 a5 a6 a7 w0 w1 w2 w3 w4 w5 w6 w7
r0
r1
r2
r3
r4
r5
r6
r7
SNCL t su(i)(SNCL) write sequence: SNDA read sequence: SNDA driven by master SNDA driven by SAA4998H a6
50 % t h(i)(SNCL) a7
50 %
50 %
w0
w1
a6
a7 t o(en) t h(o) r0 t d(o) 10 % t d(o)
coc004
90 %
r1
Fig.7 SNERT interface timing diagram.
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Philips Semiconductors
Product specification
Field and line rate converter with noise reduction and embedded memory
Table 1 YUV formats FORMAT(2)(3) 4:1:1 Yx7 Yx6 Yx5 Yx4 Yx3 Yx2 Yx1 Yx0 UVx7 UVx6 UVx5 UVx4 UVx3 UVx2 UVx1 UVx0 Notes 1. Digit x refers to different I/O buses: a) A = input from 1st field memory b) F = main output c) G = 2nd output for matrix purposes. 2. The first index digit defines the sample number and the second defines the bit number. 3. X = don't care or not available. Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 U07 U06 V07 V06 X X X X Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 U05 U04 V05 V04 X X X X Y27 Y26 Y25 Y24 Y23 Y22 Y21 Y20 U03 U02 V03 V02 X X X X Y37 Y36 Y35 Y34 Y33 Y32 Y31 Y30 U01 U00 V01 V00 X X X X Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 U07 U06 U05 U04 U03 U02 U01 U00 4:2:2 Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 V07 V06 V05 V04 V03 V02 V01 V00
SAA4998H
I/O PIN(1)
4 : 2 : 2 DPCM Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 UC03 UC02 UC01 UC00 X X X X Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 VC03 VC02 VC01 VC00 X X X X
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Philips Semiconductors
Product specification
Field and line rate converter with noise reduction and embedded memory
11 PACKAGE OUTLINE
QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SAA4998H
SOT317-2
c
y X
80 81
51 50 ZE
A
e E HE A A2 A1 (A 3) Lp bp 100 1 wM D HD ZD B vM B 30 vM A 31 detail X L
wM pin 1 index
e
bp
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.2 A1 0.25 0.05 A2 2.90 2.65 A3 0.25 bp 0.40 0.25 c 0.25 0.14 D (1) 20.1 19.9 E (1) 14.1 13.9 e 0.65 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 v 0.2 w 0.15 y 0.1 Z D (1) Z E(1) 0.8 0.4 1.0 0.6 7 o 0
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT317-2 REFERENCES IEC JEDEC MO-112 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-25
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Philips Semiconductors
Product specification
Field and line rate converter with noise reduction and embedded memory
12 SOLDERING 12.1 Introduction to soldering surface mount packages
SAA4998H
To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 12.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 12.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: * below 225 C (SnPb process) or below 245 C (Pb-free process) - for all BGA, HTSSON-T and SSOP-T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages. * below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 12.3 Wave soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems.
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Philips Semiconductors
Product specification
Field and line rate converter with noise reduction and embedded memory
12.5 Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) BGA, HTSSON..T(3), LBGA, LFBGA, SQFP, SSOP..T(3), TFBGA, USON, VFBGA DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(5), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L(8), PMFP(9), WQCCN..L(8) Notes not suitable not suitable(4) suitable not not recommended(5)(6) recommended(7)
SAA4998H
SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable suitable not suitable
not suitable
1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. 4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. 9. Hot bar or manual soldering is suitable for PMFP packages. 12.6 Additional soldering information
The package QFP100 (lead-free; SOT317GC11, subpackage of the SOT317-2) is granted the Moisture Sensitivity Level (MSL) 3. Soldering temperature of > 215 C is recommended or RMA flux.
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Philips Semiconductors
Product specification
Field and line rate converter with noise reduction and embedded memory
13 DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION
SAA4998H
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data Qualification
III
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 14 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 15 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
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Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2004
SCA76
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R24/01/pp39
Date of release: 2004
Feb 18
Document order number:
9397 750 12217

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